ICS527R-01ILF Datasheet, PDF (6/11 Pages) Integrated Device Technology – CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
VDD
0.01 F
125 MHz
25 MHz
R5
R6
DIV2
S0
S1
VDD
ICLK
FBIN
GND
OECLK2
2XDRIVE
F0
F1
F2
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
F6
F5
F4
F3
0.01 F
0.01 F
INA
QA0
QA1
QA2
VDD
VDD
QA3
QA4
GND
GND
QA5
QA6
QA7
OE
INB
QB0
QB1
QB2
VDD
VDD
QB3
QB4
GND
GND
QB5
QB6
QB7
VDD
0.01 F
0.01 F
The layout design above produces the waveforms shown below.
Note: Series terminating resistors are not shown.
125 MHz,
ICLK
25 MHz,
QA0-7
50 MHz,
QB0-7
Using the equation for selecting dividers gives:
(FDW + 2)
25 MHz = 125 MHz x
(RDW + 2)
If FDW = 0, then RDW = 8. This gives the required divide-by-5 function. Setting pin DIV2 = 1 gives both a
25 MHz and a 50 MHz output from the ICS527-01. The FBIN pin is connected to the QA7 output of the
MK74CB218. This aligns all the outputs of the MK74CB218 with the 25 MHz input since the ICS527-01
aligns rising edges on the ICLK and FBIN pins. The propagation delay of the buffer is compensated by the
PLL.
In this example, series termination resistors have been omitted for clarity but should be used on all clock
outputs.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 6
ICS527-01 REV G 051310