ICS527R-01ILF Datasheet, PDF (1/11 Pages) Integrated Device Technology – CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
DATASHEET
ICS527-01
Description
The ICS527-01 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. A SYNC
pulse indicates when the rising clock edges are aligned
with zero skew. Using Phase-Locked Loop (PLL)
techniques, the device accepts an input clock up to 200
MHz and produces an output clock up to 160 MHz.
The ICS527-01 aligns rising edges on ICLK and FBIN
at a ratio determined by the reference and feedback
dividers.
For configurable clocks that do not require zero delay,
use the ICS525.
Features
• Packaged as 28-pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• Pin configurable multiplication/division ratio
• Slices frequency or period
• SYNC pulse output indicates aligned edges
• Input clock frequency of 600 kHz to 200 MHz
• Output clock frequencies up to 160 MHz
• Very low jitter
• Duty cycle of 45/55 up to 160 MHz
• Operating voltage of 3.3V
• Pin selectable drive strength
• Multiple outputs available when combined with
fanout buffers
• Industrial temperature version available
• Pb (lead) free package
Block Diagram
ICLK
R6:R0
7
Reference
Divider
FBIN
Feedback
Divider
PDTS
OECLK2
7
F6:F0
PDTS
S1:S0
2
GND
2
VDD
2
2xDRIVE
PLL
SYNC
Divide
by 2
PDTS
1
0
DIV2
CLK1
CLK2
Feedback can
come from
CLK1 or CLK2
(not both)
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 1
ICS527-01 REV G 051310