ICS527R-01ILF Datasheet, PDF (5/11 Pages) Integrated Device Technology – CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the 1x
output drive is selected.T
VDD
0.01 F
40 MHz
R5
R6
DIV2
S0
S1
VDD
ICLK
FBIN
GND
OECLK2
2XDRIVE
F0
F1
F2
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
F6
F5
F4
F3
0.01 F
33
33
50 MHz
SYNC
Note: The series termination resistor is located before the feedback trace.
This will give the following waveforms:
40 MHz
ICLK
50 MHz
CLK1
SYNC
CLK2
Multiple Output Example
In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies
of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the
MK74CB218 which has dual 1 to 8 buffers with low pin-to-pin skew.
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 5
ICS527-01 REV G 051310