8T49N283 Datasheet, PDF (9/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N283 Datasheet
Output Phase Control on Switchover
When the 8T49N283 switches between input references, enters or
leaves the holdover state for either PLL, there are two options on how
the output phase can be controlled in these events: phase-slope
limiting or fully hitless switching (sometimes called phase build-out)
may be selected. The SWMODEn bit selects which behavior is to be
followed for PLLn.
If fully hitless switching is selected, then the output phase will remain
unchanged under any of these conditions. Note that fully hitless
switching is not supported when external loopback is being used.
Fully hitless switching should not be used unless all input references
are in the same clock domain. Note that use of this mode may
prevent an output frequency and phase from being able to trace its
alignment back to a primary reference source.
If phase-slope limiting is selected, then the output phase will adjust
from its previous value until it is tracking the new condition at a rate
dictated by the SLEWn[1:0] bits. Phase-slope limiting should be used
if all input references are not in the same clock domain or users wish
to retain traceability to a primary reference source.
Output Phase Alignment
The device has a programmable output to output phase alignment for
each of the eight output dividers. After power-up and the PLLs have
achieved lock, the device will be in a state where the outputs are
synchronized with a deterministic offset relative to each other.After
synchronization, the output alignment will depend on the particular
configuration of each output according to the following rules. The
step size is defined as the period of the clock to that divider:
1) Only outputs derived from the same source will be aligned with
each other. 'Source' means the reference selected to drive the output
divider as controlled by the CLK_SELn bit for each output.
2) For integer dividers (Q[0:1], Q[4:7]) when both divider stages are
active, edges are aligned. This case is used as a baseline to compare
the other cases here.
3) For integer dividers where the 1st-stage divider is bypassed (only
Q[4:7] support this), coarse delay adjustments can’t be performed.
The output phase will be one step earlier than in Case 2.
4) Fractional output dividers (Q2 or Q3) do not guarantee any specific
phase on power-up or after a synchronization event.
5) Integer dividers using Q2 or Q3 as a source (Q[4:7] support this
option) will be aligned to their source divider's output (Q2 or Q3).
Note that the output skews described above are not included in any
of the phase adjustments described here.
Once the device is in operation, the outputs associated with each
PLL may have their phase adjustments re-synced in one of two ways:
1) If the PLL becomes unlocked, the coarse phase adjustments will
be reset and the fine phase adjustments will be re-loaded once it
becomes locked again.
2) Toggling of a register bit for either PLL (PLLn_SYN bits in register
00A8h) may also be used to force a re-sync / re-load for outputs
associated with that PLL.
The user may apply adjustments that are proportional to the period
of the clock source each output divider is operating from. For
example, if the divider associated with Output Q3 is running off PLL0,
which has a VCO frequency of 4GHz, then the appropriate period
would be 250ps. The output phase may be adjusted in these steps
across the full period of the output.
• Coarse Adjustment: all Output Dividers may have their phase
adjusted in steps of the source clock period. For example a
4GHz VCO gives a step size of 250ps. The user may request an
adjustment of phase of up to 31 steps using a single register
write. The phase will be adjusted by lengthening the period of
the output by 250ps at a time. This process will be repeated
every four output clock periods until the full requested
adjustment has been achieved. A busy signal will remain
asserted in the phase delay register until the requested
adjustment is complete. Then a further adjustment may be
setup and triggered by toggling the trigger bit.
• Fine Adjustment: For the Fractional Output Dividers associated
with the Q2 and Q3 outputs, the phase of those outputs may be
further adjusted with a granularity of 1/16th of the VCO period.
For example a 4GHz VCO frequency gives a granularity of
16ps. This is performed by directly writing the required offset
(from the nominal rising edge position) in units of 1/16th of the
output period into a register. Then the appropriate PLLn_SYN
bit must be toggled to load the new value. Note that toggling this
bit will clear all Coarse Delays for all outputs associated with
that PLL, so Fine Delays should be set first, before Coarse
Delays. The output will then jump directly to that new offset
value. For this reason, this adjustment should be made as the
output is initially programmed or in High-Impedance.
Each output has the capability of being inverted (180 degree phase
shift).
Jitter and Wander Tolerance
The 8T49N283 can be used as a line card device and therefore is
expected to tolerate the jitter and wander output of a timing card PLL
(e.g IDT82V3390).
©2016 Integrated Device Technology, Inc.
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Revision H, October 26, 2016