8T49N283 Datasheet, PDF(55/77 Page) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

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8T49N283 Datasheet, PDF (55/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

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8T49N283 Datasheet

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.ï

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1ï

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS

(High Band) and 3.0ps RMS for tREFCLK_LF_RMS RMS (Low Band).ï

NOTE 3: RMS jitter after applying system transfer function for the Common Clock Architecture. This specification is based on the PCI Express

Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. ï

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.ï

NOTE 5: Outputs configured for LVPECL mode. Fox 277LF-40-18 crystal used with doubler logic enabled.

Typical Phase Noise at 156.25MHz

Offset Frequency (Hz)

Revision H, October 26, 2016

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