8T49N283 Datasheet, PDF (34/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N283 Datasheet
Table 6L. Output Clock Phase Adjustment Control Register Bit Field Locations and Descriptions
Output Clock Phase Adjustment Control Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
009D
CRSE_TRG[7:0]
009E
Rsvd
COARSE0[4:0]
009F
Rsvd
COARSE1[4:0]
00A0
Rsvd
COARSE2[4:0]
00A1
Rsvd
COARSE3[4:0]
00A2
Rsvd
COARSE4[4:0]
00A3
Rsvd
COARSE5[4:0]
00A4
Rsvd
COARSE6[4:0]
00A5
Rsvd
COARSE7[4:0]
00A6
Rsvd
FINE2[3:0]
00A7
Rsvd
FINE3[3:0]
Bit Field Name
CRSE_TRG[7:0]
COARSEm[4:0]
FINEm[3:0]
Rsvd
Output Clock Phase Adjustment Control Control Register Block Field Descriptions
Field
Type
R/W
Default Value
00h
Description
Trigger Coarse Phase Adjustment for output Qm, nQm by amount specified in
COARSEm[4:0] register upon 01 transition of this Trigger register bit. Please ensure the
PA_BUSYm status bit is 0 before triggering another adjustment cycle on that particular
output. Trigger bit must be returned to 0 before another delay cycle can be triggered.
R/W
00000b
Number of periods to be inserted when Trigger happens. Relevant clock period is
determined by the clock source selected for output Qm, nQm in its CLK_SELm register field.
Number of 1/16ths of the relevant clock period to add to the phase of output Qm, nQm (m =
2, 3). Relevant clock period is determined by the clock source selected for output Qm, nQm
R/W
0000b
in its CLK_SELm register field. The PLLn_SYN bit for the PLL driving the output divider for
the output in question must be toggled to make this value take effect. Note that toggling the
PLLn_SYN bit will clear all Coarse delay values and so Fine delay should be set first.
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
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Revision H, October 26, 2016