8T49N283 Datasheet, PDF (75/77 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N283 Datasheet
ERRATA
Errata # 1: EEPROM CRC Check Failure
Errata: if the UFT++ attempts to load its initial configuration from an external EEPROM and the CRC check fails, the serial port will not
complete write operations and will only respond to reads with values of 0 until device is reset via nRST pin.
- if no EEPROM access is attempted, no EEPROM is found or the EEPROM read succeeds there are no issues
- The CRC failure condition can be detected by reading the Global Interrupt Status Register at address 21Fh. If the nEEP_CRC bit is low,
then the device's serial port is now in the failed state
- if the device is also programmed to load its registers from the internal One-Time Programmable memory, those register settings will be
correctly loaded and used.
Work-Around: by reading the nEEP_CRC bit, this condition can be detected. Once detected, the user may attempt to retry the EEPROM
load operation by asserting then releasing the nRST input pin. If the retry attempt continues to fail, then no further recovery is possible.
Note that a persistent EEPROM CRC failure indicates a corrupted configuration is present and the device could not be correctly
configured anyway.
Fix Plan: None
Errata # 2: GPIOs Can't Use Input Mode if V_CCO = 1.8V
Errata: When the V_CCO pin adjacent to a GPIO pin is set to 1.8V and the core V_CC of the chip is at 3.3V, the GPIO pin will not behave as
an input, either a General-Purpose Input or an Output Enable. Mappings are according to the following relationships:
GPIO0 / V_CCO3
GPIO1 / V_CCO3
GPIO2 / V_CCO4
GPIO3 / V_CCO7
Work-Around: Ensure that voltage used on V_CCO pins is no less than V_CC - 1.6V.
Fix Plan: None
©2016 Integrated Device Technology, Inc.
75
Revision H, October 26, 2016