84427 Datasheet, PDF (9/16 Pages) Integrated Device Technology – Crystal-to-LVDS Integrated Frequency Synthesizer/Fanout Buffer

84427 DATA SHEET
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω dif-
ferential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
LVDS_Driv er
3.3V
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an 84427. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R7, C11 and C16
for clean analog supply should also be located as close to the
VDDA pin as possible.
VDD
VDD
R7
24
C11
0.1u
C16
10u
VDD
VDD
VDDA
22p
C1
X1
25MHz,18pF
C2
18p
R4 VDD
1K
F_SEL2
F_SEL1
R5 F_SEL0
1K
U1
13
14 ^VDD
15 ^VEE
16 ^PLL_SEL
17 ^VDD
18
19
VDDA
F_SEL2
20 ^XTAL_OUT
21 ^XTAL_IN
22 ^MR
23 ^F_SEL1
24 ^F_SEL0
VDD
ICS84427
12
nQ5 ₁₁
Q5 ₁₀
nQ4 ₉
Q4 ₈
nQ3
Q3
7
6
nQ2 ₅
Q2 ₄
nQ1 ₃
Q1 ₂
nQ0 ₁
Q0
Zo = 50
R1
100
Zo = 50
RU1
1K
RU2
SP
RU3
1K
F_SEL2
F_SEL1
F_SEL0
VDD=3.3V
VDD
(U1,13)
(U1,16)
(U1,24)
RD1
SP
RD2
1K
RD3
SP
e.g. F_SEL[2:0]=101
SP = Spare, Not Installed
C6
0.1u
C5
0.1u
C3
0.1u
+
-
LVDS_input
REVISION B 5/6/15
FIGURE 5A. 84427 SCHEMATIC EXAMPLE
9
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER