84427 Datasheet, PDF (1/16 Pages) Integrated Device Technology – Crystal-to-LVDS Integrated Frequency Synthesizer/Fanout Buffer

Crystal-to-LVDS Integrated
Frequency Synthesizer/Fanout Buffer
84427
DATASHEET
GENERAL DESCRIPTION
T h e 8 4 4 2 7 i s a C r y s t a l - t o - LV D S Fr e q u e n c y
Synthesizer/Fanout Buffer. The output frequency can be
programmed using the frequency select pins. The low phase
noise characteristics of the 84427 make it an ideal clock source
for 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, OC3 and
OC12 applications.
FUNCTION TABLE
F_XTAL MR
X
1
19.44MHz 0
19.44MHz 0
19.44MHz 0
19.44MHz 0
25MHz 0
25MHz 0
25MHz 0
25MHz 0
25.5MHz 0
Inputs
F_SEL2
X
1
1
1
1
0
0
0
0
0
F_SEL1
X
0
0
1
1
0
0
1
1
0
F_SEL0
X
0
1
0
1
0
1
0
1
1
Output
Frequency
F_OUT
LOW
77.76MHz
155.52MHz
311.04MHz
622.08MHz
78.125MHz
156.25MHz
312.5 MHz
625MHz
159.375MHz
FEATURES
• Six LVDS outputs
• Crystal oscillator interface
• Output frequency range: 77.76MHz to 625MHz
• Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
• RMS phase jitter at 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 3.4ps (typical)
Phase noise:
Offset
Noise Power
100Hz ..................-95 dBc/Hz
1kHz ................-110 dBc/Hz
10kHz ................-120 dBc/Hz
100kHz ................-121 dBc/Hz
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS-compliant package
BLOCK DIAGRAM
XTAL_IN
XTAL_OUT
OSC
PLL
0
Output
/^{6 Q0:Q5}
1
Divider
/^{6 nQ0:nQ5}
Feedback
Divider
F_SEL2 MR PLL_SEL F_SEL1
F_SEL0
PIN ASSIGNMENT
Q0 1
nQ0 2
Q1 3
nQ1 4
Q2 ₅
nQ2 6
Q3 7
nQ3 8
Q4 9
nQ4 10
Q5 11
nQ5 12
24 VDD
23 F_SEL0
22 F_SEL1
21 ^MR
20 XTAL_IN
19 XTAL_OUT
18 F_SEL2
17 ^VDDA
16 ^VDD
15 PLL_SEL
14 GND
13 VDD
84427
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
84427 REVISION B 5/6/15
1
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