84427 Datasheet, PDF (10/16 Pages) Integrated Device Technology – Crystal-to-LVDS Integrated Frequency Synthesizer/Fanout Buffer

84427 DATA SHEET
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V_DDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital sys-
tems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge or
excessive ring back can cause system failure. The shape of the
trace and the trace delay might be restricted by the available
space on the board and the component location. While routing
the traces, the clock signal traces should be routed first and
should be locked prior to routing other signal traces.
• The differential 100Ω output traces should have the
same length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between
the clock trace pair.
• The matching termination resistors should be located
as close to the receiver input pins as possible.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL_IN) and 19 (XTAL_OUT). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
C6
C1
C5
R7
VDDA
C16
C11
X1
GND
VDD
Signals
VIA
C2
C3
U1 ICS84427
Pin1
50 Ohm Traces
FIGURE 5B. PCB BOARD LAYOUT FOR 84427
CRYSTAL-TO-LVDS
10
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
REVISION B 5/6/15