ICSSSTVA16857 Datasheet, PDF (8/9 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer

ICSSSTVA16857
From Output
Under Test
V_TT
R_L=50Ω
Test Point
C_L = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
t_inact
IDD
(see note 2)
V_DDQ/2
V_DDQ/2
V_DDQ
0V
t_act
10%
90% ^IDDH
IDDL
Voltage and Current Waveforms
Inputs Active and Inactive Times
t_w
V_IH
Input
V_REF
V_REF
V_IL
Voltage Waveforms - Pulse Duration
Timing
Input
V_ICR
V_I(pp)
Input
t_S
t_h
V_REF
V_IH
V_REF
V_IL
Voltage Waveforms - Setup and Hold Times
Timing
Input
V_ICR
V_ICR
V_I(pp)
t_PHL
t_PHL
Output
V_OH
V_TT
V_TT
V_OL
Voltage Waveforms - Propagation Delay Times
LVCMOS
V_IH
RESET#
Input
VDD/2
V_IL
t_PHL
Output
V_OH
V_TT
V_OL
Voltage Waveforms - Propagation Delay Times
Figure 1 - Parameter Measurement Information (V_DDQ = 2.5V ±0.2V)
Notes:
1. CL incluces probe and jig capacitance.
2. I_DD tested with clock and data inputs held at V_DDQ or GND, and I_O = 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V_TT = V_REF = V_DDQ/2
6. V_IH = V_REF + 310mV (AC voltage levels) for differential inputs. V_IH = V_DDQ for LVCMOS input.
7. V_IL = V_REF - 310mV (AC voltage levels) for differential inputs. V_IL = GND for LVCMOS input.
8. t_PLH and t_PHL are the same as t_pd
0932A—05/12/04
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