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ICSSSTVA16857 Datasheet, PDF (3/9 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer
ICSSSTVA16857
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous Output Current . . . . . . . . . . . . . . . ±50 mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . ±100 mA
Package Thermal Impedance3 . . . . . . . . . . . . . . . . 55°C/W
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V0 >VDDQ.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Recommended Operating Conditions - DDRI/DDR333 (PC1600, PC2100, PC2700)
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
VDD
VDDQ
VREF
VTT
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
VIL
VICR
VID
VIX
Supply Voltage
2.3
2.5
2.7
I/O Supply Voltage
2.3
2.5
2.7
Reference Voltage
1.15
1.25
1.35
Termination Voltage
VREF - 0.04
VREF
VREF + 0.04
Input Voltage
0
VDDQ
DC Input High Voltage
VREF + 0.15
AC Input High Voltage
DC Input Low Voltage
Data Inputs VREF + 0.31
VREF - 0.15
V
AC Input Low Voltage
VREF - 0.31
Input High Voltage Level
RESET#
1.7
Input Low Voltage Level
0.7
Common mode Input Range
0.97
1.53
CLK, CLK#
Differential Input Voltage
0.36
Cross Point Voltage of Differential Clock
Pair
(VDDQ/2) - 0.2
(VDDQ/2) + 0.2
IOH
High-Level Output Current
IOL
Low-Level Output Current
TA
Operating Free-Air Temperature
0
1Guaranteed by design, not 100% tested in production.
-16
mA
16
70
°C
0932A—05/12/04
3