ICSSSTVA16857 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer

ICSSSTVA16857
DDR 14-Bit Registered Buffer
Recommended Applications:
• DDR Memory Modules
• Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
• SSTL_2 compatible data registers
• DDR400 recommended (backward compatible to
DDR200/266/333)
Product Features:
• Exceeds "SSTVN16857" performance
• Differential clock signal
• Meets SSTL_2 signal data
• Supports SSTL_2 class I & II specifications
• Low-voltage operation
- V_DD = 2.3V to 2.7V
• 48 pin TSSOP package
Truth Table¹
RESET#
L
H
H
H
Inputs
CLK
CLK#
X or
X or
Floating Floating
↑
↓
↑
↓
L or H L or H
Q Outputs
D
Q
X or
Floating
L
H
H
L
L
X
Q₀₍₂₎
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
Block Diagram
CLK
CLK#
38
39
RESET# ³⁴
D1
VREF
48
35
Pin Configuration
Q1
1
48
Q2
2
47
GND
3
46
VDDQ
4
45
Q3
5
44
Q4
6
43
Q5
7
42
GND
8
41
VDDQ
9
40
Q6
10
39
Q7
11
38
VDDQ
12
37
GND
13
36
Q8
14
35
Q9
15
34
VDDQ
16
33
GND
17
32
Q10
18
31
Q11
19
30
Q12
20
29
VDDQ
21
28
GND
22
27
Q13
23
26
Q14
24
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
R
CLK
D1
1 _Q1
0932A—05/12/04
To 13 Other Channels