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ICSSSTVA16857 Datasheet, PDF (7/9 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer | |||
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ICSSSTVA16857
Timing Requirements1
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDDQ = 2.5V ± 0.2V
MIN
MAX
fclock Clock frequency
270
tSL Output slew rate
1
4
tS
Setup time, fast slew rate 2 & 4
Setup time, slow slew rate 3 & 4
Data before CLKâ , CLK#â
0.4
0.6
Th
Hold time, fast slew rate 2 & 4
Hold time, slow slew rate 3 & 4
Data after CLKâ , CLK#â
0.4
0.5
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of ⥠1V/ns.
3 - For data signal input slew rate of ⥠0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of ⥠1V/ns.
UNITS
MHz
V/ns
ns
ns
ns
ns
Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
SYMBOL
From
(Input)
To
(Output)
VDD = 2.5V ±0.2V
UNITS
MIN
TYP MAX
fmax
tPD CLK, CLK# (TSSOP)
tphl RESET#
210
MHz
Q
1.6
2.1
2.6
ns
Q
3.5
ns
Switching Characteristics - DDRI-400 (PC3200)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
SYMBOL
From
(Input)
To
(Output)
VDD = 2.6V ±0.1V
UNITS
MIN
TYP MAX
fmax
tPD CLK, CLK# (TSSOP)
tphl RESET#
210
MHz
Q
1.1
1.6
1.89
ns
Q
3.5
ns
0932Aâ05/12/04
7
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