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| DAC1617D1G0 Datasheet, PDF (8/78 Pages) Integrated Device Technology – Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating | |||
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Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
9. Characteristics
Table 5. Characteristics
VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 ï°C; RL = 50 ï; IO(fs) = 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test Min
[1]
Typ
Max
Unit
VDDA(3V3)
analog supply
voltage (3.3 V)
C
3.15
3.3
3.45
V
VDDD
digital supply
voltage
C
1.7
1.8
1.9
V
VDDA(1V8)
analog supply
voltage (1.8 V)
C [2] 1.7
1.8
1.9
V
IDDA(3V3)
analog supply Auxiliary DAC on
C
51
55
59
mA
current (3.3 V)
IDDD
digital supply fs = 983.04 67;
C
475
525
585
mA
current (1.8 V) ï´4 interpolation; no NCO;
MDS off
fs = 620 Msps;
C
400
450
500
mA
ï´2 interpolation; NCO on;
no MDS
IDDA(1V8)
analog supply fs = 983.04 Msps; 1 V (p-p) C [2] 207
218
230
mA
current (1.8 V) fs = 620 Msps; 1 V (p-p) C
207
218
230
mA
Ptot
total power
fs = 983.04 Msps;
C
-
1580
-
mW
dissipation
ï´4 interpolation; NCO off;
MDS off
fs = 983.04 Msps;
C
-
1500
-
mW
ï´4 interpolation;
5-bit NCO; MDS off
fs = 620 Msps;
ï´2 interpolation; 5-bit
NCO; MDS off
-
1370
-
mW
power-down using SPI
C
-
63
-
mW
register
Clock inputs (pins CLKP, CLKN)
Vi(clk)dif
differential clock peak-to-peak
input voltage
C
150
-
1000
mV
Ri
input resistance
Ci
input
capacitance
D
-
200
-
kï
D
-
1
-
pF
Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN, ALIGNP and ALIGNN)
Vi
input voltage
ï¼Vgpdï¼ < 50 mV[3]
Vidth
input differential ï¼Vgpdï¼ < 50 mV[3]
threshold
voltage
C
825
-
C
ï100
-
1575
mV
+100
mV
Ri
input resistance
D
-
100
-
ï
Ci
input
D
-
0.8
-
pF
capacitance
pins LCKP and LCKN
D
-
0.9
-
pF
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 â 2 July 2012
© IDT 2012. All rights reserved.
8 of 78
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