DAC1617D1G0 Datasheet, PDF(60/78 Page) Integrated Device Technology – Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

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DAC1617D1G0 Datasheet, PDF (60/78 Pages) Integrated Device Technology – Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

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Integrated Device Technology

DAC1617D1G0

Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating

Table 44. MDS status registers (address 09h to 0Ah) bit description â¦continued

Default values are shown highlighted.

Address Register

Bit

Symbol

Access Value Description

0Ah

MDS_STATUS1 5

ADD_ERR

adjustment delay error detection

delay offset cannot be applied in

available range

4 to 3 MDS_EN_PHASE[1:0] R

MDS enable phase

enable phase = 0

enable phase = 1 (only for ï´2)

enable phase = 2

(only for ï´2 and ï´4)

enable phase = 3 (only for ï´2)

MDS_PRERUN

MDS-PRERUN phase active flag

false

true

MDS_LOCKOUT

MDS_LOCKOUT detected flag

false

true

MDS_LOCK

MDS_LOCK flag

false

true

Table 45. Interrupt control register (address 0Bh) bit description

Default values are shown highlighted.

Bit Symbol

Access Value Description

INTR_CTRL

R/W

internal interrupt and flags clearance

disabled

enabled

2 to 0 INTR_MON_DCLK_RANGE R/W

Interrupt condition as related to the DCLK monitoring

mon_dclk_flag when mon_dclk drifts to (1 or 5)

(detect small drift)

mon_dclk_flag when mon_dclk drifts to (2 or 4)

(detect large drift)

mon_dclk_flag when mon_dclk drifts to (3)

(detect maximum drift)

mon_dclk_flag disabled

DAC1617D1G0 3

Preliminary data sheet

Rev. 03 â 2 July 2012

60 of 78

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