DAC1617D1G0 Datasheet, PDF (34/78 Pages) Integrated Device Technology – Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
During the whole alignment process, the MDS controller tries to adjust the delay to get the
internal copy signal aligned to the external MDS signal. Once aligned, the MDS signal is
not required anymore. it can be switched off at system level. The alignment is done just in
front of the analog DACs cores ensuring the 1 DAC clock sample accuracy.
At the end of the MDS process, the MDS circuitry is disabled to avoid any analog
disturbances.
The MDS feature can be used in two modes:
• All slaves mode
• Master/slaves mode
The mode can be set using the MD_MASTER bit of register MDS_MAIN (see Table 36).
10.13.1.1 MDS in All slaves mode
In this mode, each device uses its ALIGN pins signal to identify the LVDS data flow start
(see Figure 23). The FPGA(s) has(have) to generate these ALIGN signals.
The FPGA is also used to generate the different MDS reference signals to enable the
DAC1617D1G0 devices to do the synchronization of the output. Use this mode when two
or more DAC1617D1G0 devices must be synchronized.
Figure 25 shows the MDS All slave mode schematic.
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Fig 25. MDS in All slaves mode
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DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
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