DAC1617D1G0 Datasheet, PDF (67/78 Pages) Integrated Device Technology – Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.8 Page A bit definition detailed description
The tables in this section contain detailed descriptions of the page A registers.
Table 54. Register MAIN_CNTRL (address 00h)
Default values are shown highlighted.
Bit
Symbol
Access
4
LD_PD
R/W
Value
3
PD_CNTRL
2
CAL_CNTRL
1
RST_DCLK
0
RST_LCLK
0
1
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
1
Description
LVDS interface power-down (control possible only
when PD_CNTRL = 1)
switched on
switched off
power-down modes controlled by
DCMSU block
SPI registers
compensation delay controlled by
DCMSU block (automatic calibration)
SPI registers (manual control)
reset DCLK
disable
enable
reset LVDS clock
disable
enable
Table 55. Register MAN_LDCLKDEL (address 01h)
Default values are shown highlighted.
Bit
Symbol
Access
Value
3 to 0 LDCLK_DEL[3:0]
R/W
-
Description
LVDS clock compensation delay (control only if
CAL_CNTRL = 1)
4-bit compensation delay for LVDS clock
Table 56. Register DBG_LVDS (address 02h)
Default values are shown highlighted.
Bit
Symbol
Access
3
SBER
R/W
2 to 0 RESERVED
R/W
Value
0
1
000
Description
simple BER control
no action
simple BER active
reserved
DAC1617D1G0 3
Preliminary data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
67 of 78