DAC1617D1G0 Datasheet, PDF (65/78 Pages) Integrated Device Technology – Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

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10.22.7 Page A register allocation map
Table 53 shows an overview of all registers on page A (0Ah in hexadecimal).
Table 53.
Address
0 00h
Page_0A register allocation map
Register name
R/W
Bit 7
MAIN_CNTRL
R/W
-
Bit 6
-
1 01h MAN_LDCLKDEL R/W
-
-
2 02h DBG_LVDS
R/W
-
-
4 04h RST_EXT_LDCLK R/W
5 05h RST_EXT_DCLK R/W
6 06h DCMSU_PREDIV R/W
8 08h LD_POL_LSB
R/W
9 09h LD_POL_MSB
R/W
10 0Ah LD_CNTRL
R/W PARITYC DESCRAMBLE
11 0Bh MISC_CNTRL
R/W SR_CDI RESERVED
12 0Ch I_DC_LVL_LSB R/W
13 0Dh I_DC_LVL_MSB R/W
14 0Eh Q_DC_LVL_LSB R/W
15 0Fh Q_DC_LVL_MSB R/W
16 10h IO_MUX0
R/W
Bit 5
-
-
Bit definition
Bit 4
Bit 3
LD_PD
PD_CNTRL
-
Bit 2
Bit 1
CAL_
CNTRL
RST_
DCKL
LDCLK_DEL[3:0]
Bit 0
RST_
LCKL
-
-
SBER
RESERVED
RST_EXT_LCLK_TIME[7:0]
RST_EXT_DCLK_TIME[7:0]
DCMSU_PREDIVIDER[7:0]
LD_POL[7:0]
LD_POL[15:8]
SEL_EN[1:0]
WORD_SWAP
LDAB_
SWAP
I_LEV_
CNTRL[1:0]
Q_LEV_CNTRL[1:0]
I_DC_LEVEL[7:0]
IQ_
EDGE_
FORMAT LDCLK
CDI_MODE[1:0]
I_DC_LEVEL[15:8]
Q_DC_LEVEL[7:0]
Q_DC_LEVEL[15:8]
IO_SELECT0[7:0]
Default
Bin Hex
0000 03h
0011
0000 00h
0000
0000 00h
0000
0011 3Fh
1111
0010 20h
0000
0001 1Dh
1101
0000 00h
0000
0000 00h
0000
0000 03h
0011
0000 00h
0000
0000 00h
0000
1000 80h
0000
0000 00h
0000
1000 80h
0000
1111 FFh
1111