932QL456 Datasheet, PDF (8/23 Pages) Integrated Device Technology – Low-Power CK420BQ Derivative for PCIe

932SQL456 DATASHEET
Functionality Tables
932SQL456 Functionality
CPU
100
SRC
100
PCI
33.33
REF
14.318
NS_SAS
NS_SRC
100.00
DOT96
96.00
USB
48.00
MHz
932SQL456 Power Down Functionality
CKPWRGD#/PD
1
Differential
Outputs
Low/Low
Single-
ended
Outputs
Low
Single-
ended
Outputs
w/Latch
Low¹
0
Running
1. Single-ended outputs with a Latch will be Hi-Z until
the first application of CKPWRGD#.
Clock AC Tolerances
CPU, SRC
PPM tolerance 100
Cycle to Cycle Jitter 50
Spread 0.00%
NS_SAS,
NS_SRC
100
50
0.00%
PCI
100
250
0.00%
DOT96
100
50
0
48MHz
100
250
0.00%
REF
100
250
0.00%
ppm
ps
%
Clock Periods–Outputs
SSC OFF
CPU,
SRC,
NS_SAS,
NS_SRC
PCI
DOT96
48MHz
REF
Center
Freq.
MHz
100.000
33.333
96.000
48.000
14.318
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
-c2c jitter
-SSC
- ppm
AbsPer ^{Short-Term Long-Term}
Min
Average Average
Min
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
9.94900
9.99900 10.00000 10.00100
29.74700
10.36563
20.58125
69.78429
29.99700
10.41563
20.83125
69.83429
30.00000
10.41667
20.83333
69.84128
30.00300
10.41771
20.83542
69.84826
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100 ns
1,2
30.25300 ns 1,2
10.46771 ns 1,2
21.08542 ns 1,2
69.89826 ns 1,2
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz.}
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES
8
REVISION B 09/29/15