932QL456 Datasheet, PDF (4/23 Pages) Integrated Device Technology – Low-Power CK420BQ Derivative for PCIe

932SQL456 DATASHEET
64VFQFPN Pin Descriptions
PIN #
PIN NAME
1 GNDPCI
2 VDDPCI
3 PCI4_2x
4 PCI3_2x
5 PCI2_2x
6 PCI1_2x
7 PCI0_2x
8 GNDPCI
9 VDDPCI
10 VDD48
11 48M_2x
12 GND48
13 GND96
14 DOT96_Z85T
15 DOT96_Z85C
16 AVDD96
17 TEST_MODE
18 CKPWRGD#/PD
19 VDDSRC
20 SRC0_Z85T
21 SRC0_Z85C
22 GNDSRC
23 SRC1_Z85C
24 SRC1_Z85T
25 SRC2_Z85C
26 SRC2_Z85T
27 VDDSRC
28 AVDD_SRC
29 GNDSRC
30 NC
31 NS_SRC0_Z85C
32 NS_SRC0_Z85T
33 NS_SRC1_Z85C
34 NS_SRC1_Z85T
35 VDDNS
36 GNDNS
37 NS_SAS0_Z85C
38 NS_SAS0_Z85T
TYPE
DESCRIPTION
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
PWR 3.3V power for the 48MHz output and logic
OUT 3.3V 48MHz output
PWR Ground pin for 48MHz output and logic.
PWR Ground pin for DOT96 output and logic.
OUT
True clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential 96MHz output. Internally terminated to}
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
IN ^{TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test}
mode. Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
IN Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
PWR 3.3V power for the SRC outputs and logic
OUT ^{True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR Ground pin for SRC outputs and logic.
OUT ^{Complementary clock of low-power push-pull differential SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm}
transmission lines with no external components.
OUT ^{Complementary clock of low-power push-pull differential SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm}
transmission lines with no external components.
PWR 3.3V power for the SRC outputs and logic
PWR 3.3V power for the SRC PLL analog circuits
PWR Ground pin for SRC outputs and logic.
N/A No Connection.
OUT ^{Complementary clock of low-power push-pull differential non-spreading SRC output. Internally}
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to}
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the Non-Spreading differential outputs outputs and logic
PWR Ground pin for non-spreading differential outputs and logic.
OUT
Complementary clock of low-power push-pull differential non-spreading SAS output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT ^{True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to}
drive 85ohm transmission lines with no external components.
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES
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REVISION B 09/29/15