932QL456 Datasheet, PDF (11/23 Pages) Integrated Device Technology – Low-Power CK420BQ Derivative for PCIe

932SQL456 DATASHEET
DC Electrical Characteristics–CPU, SRC, NS_SAS, NS_SRC, DOT96 LP-HCSL
Outputs
TA = T_AMB; Supply Voltage VDDx = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Slew rate
dV/dt
Scope averaging on
2
Slew rate matching
∆dV/dt
Slew rate matching, Scope
averaging on
Rise/Fall Time Matching
∆Trf
Rise/fall matching, Scope
averaging off
Voltage High
VHigh
Statistical measurement on
660
single-ended signal using
Voltage Low
VLow
oscilloscope math function.
-150
(Scope averaging on)
Max Voltage
Vmax Measurement on single ended
Min Voltage
Vmin
signal using absolute value.
-300
TYP
3.3
11.1
9.0
845
122
1026
-22
MAX
4.5
20
125
UNITS NOTES
V/ns 1, 2, 3
% 1, 2, 4
ps 1, 8, 9
850
mV
150
1150
1, 7
mV
1, 7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250
482
550
mV
1, 5
Crossing Voltage (var) ^∆-Vcross
Scope averaging off
22
140
mV
1, 6
1_{Guaranteed by design and characterization, not 100% tested in production. ZO=85Ω (differential impedance).}
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window}
around differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window}
centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the
voltage thresholds the oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential}
rising edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max}
(V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than
7 _{Includes overshoot and undershoot.}
8 _{Measured from single-ended waveform}
9 _{Measured with scope averaging off, using statistics function. Variation is difference between min and max.}
Electrical Characteristics–48MHz
TA = T_AMB; Supply Voltage VDDx = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
V_OH
Output Low Voltage
V_OL
I_OH = -1 mA
2.4
I_OL = 1 mA
Clock High Time
T_HIGH
1.5V
8.094
Clock Low Time
T_LOW
1.5V
7.694
Edge Rate
t_{slewr/f_USB}
Rising/Falling edge rate
1
Duty Cycle
d_t1
V_T = 1.5 V
45
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
See "Power Supply and Test Loads" page for termination circuits
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured between 0.8V and 2.0V}
TYP
1.7
50.4
29
MAX
0.55
10.036
9.836
2
55
250
UNITS NOTES
V
V
ns
1
ns
1
V/ns 1,2
%
1
ps
1
REVISION B 09/29/15
11
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES