844008I-46 Datasheet, PDF (8/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

844008I-46 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
CRYSTAL INPUT INTERFACE
The 844008I-46 has been characterized with an 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
X1
18pF Parallel Crystal
C1
27pF
XTAL_IN
C2
27pF
XTAL_OUT
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be done
in one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and
R2 can be 100Ω. This can also be accomplished by removing R1
and making R2 50Ω.
VDD
VDD
R1
Ro
Rs
.1uf
Zo = 50
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
FEMTOCLOCK™ CRYSTAL-TO-LVDS
8
CLOCK GENERATOR
REVISION A 11/6/15