844008I-46 Datasheet, PDF (7/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

PARAMETER MEASUREMENT INFORMATION, CONTINUED
844008I-46 DATA SHEET
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The 844008I-46
provides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V , V , and
DD
DDA
V should be individually connected to the power supply
DDO
plane through vias, and 0.01µF bypass capacitors should be
used for each pin. Figure 1 illustrates this for a generic V pin
CC
and also shows that V requires that an additional 10Ω resistor
DDA
along with a 10µF bypass capacitor be connected to the V pin.
DDA
FIGURE 1. POWER SUPPLY FILTERING
REVISION A 11/6/15
7
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR