844008I-46 Datasheet, PDF (10/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

844008I-46 DATA SHEET
SCHEMATIC LAYOUT
Figure 6 shows an example of 844008I-46 application
schematic. In this example, the device is operated at
V = V = 3.3V. The 18pF parallel resonant 25MHz crystal
DD
DDO
is used. The C1 = 27pF and C2 = 27pF are recommended
for frequency accuracy. For different board layout, the C1
and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVDS for receiver without built-in
termination are shown in this schematic.
VDD
C2
27pF
X1
25MHz
18pF
C1
27pF
Q0
nQ0
VDDO
Q1
nQ1
Q2
nQ2
C7
0.1uF
U1
1
2 ^Q0
3
4
nQ0
GND
5 ^Q1
6 ^nQ1
7 ^VDDO
8 ^Q2
nQ2
C5
0.1uF
VDDA
VDD
GND
FREQ_SEL
C3
0.01u
R1
C4
10
10uF
Q7
Zo = 50 Ohm
+
R2
Zo = 50 Ohm
100
nQ7
-
24
nc ₂₃
OE
OE
GND
22
21
nQ7
VDDO
nQ7 ₂₀
Q7
Q7 ₁₉
VDDO ₁₈
nQ6
nQ6 ₁₇
Q6
C6
Q6
0.1uF _{VDD= VDDO=3.3V}
ICS844008I-46
Logic Control Input Examples
Set Logic
VDD
Input to
'1'
RU1
1K
Set Logic
VDD
Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDDO
C8
0.1uF
Zo = 50 Ohm
Q6
R3
50
+
C9
0.1uF
-
R4
Zo = 50 Ohm
50
nQ6
Alternate
LVDS
Termination
FIGURE 6. 844008I-46 SCHEMATIC LAYOUT
FEMTOCLOCK™ CRYSTAL-TO-LVDS
10
CLOCK GENERATOR
REVISION A 11/6/15