844008I-46 Datasheet, PDF (2/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

844008I-46 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0 Output
Differential output pair. LVDS interface levels.
3, 11, 22, 32 GND
Power
Power supply ground.
4, 5
Q1, nQ1 Ouput
Differential output pair. LVDS interface levels.
6, 14, 19
7, 8
V
DDO
Q2, nQ2
Power
Output
Output supply pins.
Differential output pair. LVDS interface levels.
9, 10
Q3, nQ3 Output
Differential output pair. LVDS interface levels.
12, 13
Q4, nQ4 Output
Differential output pair. LVDS interface levels.
15, 16
Q5, nQ5 Output
Differential output pair. LVDS interface levels.
17, 18
Q6, nQ6 Output
Differential output pair. LVDS interface levels.
20, 21
23
24, 28, 29
Q7, nQ7
OE
nc
Output
Input
Unused
Pullup
Differential output pair. LVDS interface levels.
Output enable pin. When LOW, outputs are disabled. When HIGH. outputs
are enabled. LVCMOS/LVTTL interface levels. See Table 3.
No connect.
25
V
Power
DDA
Analog supply pin.
26
FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
27
V
Power
DD
30,
31
XTAL_IN,
XTAL_OUT
Input
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
IN
R
PULLDOWN
R
PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. OE FUNCTION TABLE
Inputs
OE
1
0
Outputs
Q[0:7]/nQ[0:7]
Enabled (default)
Hi-Z
FEMTOCLOCK™ CRYSTAL-TO-LVDS
2
CLOCK GENERATOR
REVISION A 11/6/15