844003I-04 Datasheet, PDF (8/19 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Frequency Synthesizer

844003I-04 Datasheet
AC Electrical Characteristics
Table 6. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Output Divider = ÷1
Output Divider = ÷2
f_OUT
Output Frequency
Output Divider = ÷3
Output Divider = ÷4
Output Divider = ÷5
Output Divider = ÷8
tsk(b) Bank Skew; NOTE 1
NOTE 2, 3
Outputs @ Same Frequency
tsk(o) Output Skew NOTE 2, 3, 4 QB  1, Outputs @ Different Frequencies
NOTE 2, 3, 5 QB = 1, Outputs @ Different Frequencies
625MHz, (1.875MHz - 20MHz)
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 6
312.5MHz, (1.875MHz - 20MHz)
250MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
100MHz, (1.875MHz - 20MHz)
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Output Divider  ÷1
Output Divider = ÷1
Minimum
490
245
163.33
122.5
98
61.25
150
48
44
Typical
0.34
0.34
0.42
0.50
0.41
Maximum
680
340
226.67
170
136
85
25
50
250
525
550
52
56
Units
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Characterized with DIV_SELA[1:0] = 11 and DIV_SELB[1:0] = 11.
NOTE 5: Characterized with DIV_SELA[1:0] = 00 and DIV_SELB[1:0] = 00.
NOTE 6: Please refer to the Phase Noise Plots.
©2016 Integrated Device Technology, Inc.
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Revision C, November 10, 2016