844003I-04 Datasheet, PDF (2/19 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Frequency Synthesizer

844003I-04 Datasheet
Table 1. Pin Descriptions
Number
1, 7, 13, 22
2,
3
4
5
6
8, 26, 29, 30
9
10
11
12
14
15
16
17
18, 19
20, 21
23, 24
25
27, 31
28
32
Name
GND
XTAL_IN
XTAL_OUT
XTAL_SEL
VCO_SEL
MR
nc
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
FB_DIV
OEB
OEA
V_{DDO_B}
nQB1, QB1
nQB0, QB0
nQA0, QA0
V_{DDO_A}
V_DD
V_DDA
REF_CLK
Type
Power
Input
Input
Pullup
Input
Pullup
Input Pulldown
Unused
Input
Input
Input
Input
Pulldown
Pullup
Pulldown
Pullup
Input Pulldown
Input
Pullup
Input
Pullup
Power
Output
Output
Output
Power
Power
Power
Input Pulldown
Description
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
Crystal select pin. Selects between the single-ended REF_CLK or crystal interface.
Has an internal pullup resistor so the crystal interface is selected by default.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset,
(except for ÷1 state, when the device is configured as a buffer), causing the true
outputs QXx to go low and the inverted outputs nQXx to go high. When logic LOW,
the internal dividers and the outputs are enabled. MR has an internal pulldown
resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
No connect.
Division select pin for Bank A. Default = LOW. LVCMOS/LVTTL interface levels.
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
Division select pin for Bank B. Default = LOW. LVCMOS/LVTTL interface levels.
Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the output
pair on Bank B is enabled. When logic LOW, the output pair is in a high-
impedance state. Has an internal pullup resistor so the default power-up state of
the outputs is enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair on Bank A is enabled. When logic LOW, the output pair is in a high-
impedance state. Has an internal pullup resistor so the default power-up state of
the outputs is enabled. LVCMOS/LVTTL interface levels.
Output power supply pin for Bank B outputs.
Differential Bank B output pair. LVDS interface levels.
Differential Bank B output pair. LVDS interface levels.
Differential Bank A output pair. LVDS interface levels.
Output supply pin for Bank A outputs.
Core supply pins.
Analog supply pin.
Single-ended reference clock input. Has an internal pulldown resistor to pull to low
state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL
interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
2
Revision C, November 10, 2016