844003I-04 Datasheet, PDF (15/19 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Frequency Synthesizer

844003I-04 Datasheet
Schematic Example
Figure 6 shows an example of an 844003I-04 application schematic.
In this example, the device is operated at V_DD = V_{DDO _A} = V_{DDO_B}
= 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1
and C2 = 27pF are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. Two examples of LVDS for receiver
without built-in termination are shown in this schematic.
VDD
R1
VDDA
10 C6
C7
10uF
0.01u
VDD
Q1
R3
33
Driv er_LVCMOS
Zo = 50
C4
0.1uF
REF_CLK
U1
C1
27pF
X1
25M₁ H_{8 p} z_F
XTAL_SEL
C2 VCO_SEL
27pF MR
Logic Control Input Examples
1
2
3
4
GND
XTAL_IN
XTAL_OUT
5
6
7
8
XTAL_SEL
VCO_SEL
MR
GND
nc
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
VDD
C3
.1uf
VDDO_A
Zo = 50 Ohm
QA0
+
R2
Zo = 50 Ohm 100
nQA0
-
0.1uF
C5
VDD=3.3V
VDDO_A = VDDO_B=3.3V
QA0
nQA0
GND
24
23
22
21
QB0
nQB0
QB1
nQB1
20
19
18
17
QB1
VDDO_B
VDDO_B
Zo = 50 Ohm
R4
50
+
OEA
OEB
0.1uF
C8
C9
0.1uF
-
R5
Zo = 50 Ohm
50
nQB1
Alternate
LVDS
Termination
Figure 6. ICS870931I-01 Schematic Layout Example
©2016 Integrated Device Technology, Inc.
15
Revision C, November 10, 2016