844003I-04 Datasheet, PDF (11/19 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Frequency Synthesizer

Parameter Measurement Information, continued
844003I-04 Datasheet
Differential Output Voltage Setup
Offset Voltage Setup
Applications Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844003I-04 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_DD, V_DDA, V_{DDO_A} and V_{DDO_B} should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V_DD pin and also shows that V_DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V_DDA pin.
3.3V
V_DD
.01µF _10Ω
V_DDA
.01µF
10µF
Figure 1. Power Supply Filtering
Crystal Input Interface
The 844003I-04 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using an 18pF parallel resonant crystal and were chosen
to minimize the ppm error.
X1
18pF Parallel Crystal
C1
27pF
XTAL_IN
C2
27pF
XTAL_OUT
Figure 2. Crystal Input Interface
©2016 Integrated Device Technology, Inc.
11
Revision C, November 10, 2016