8413S12I-100_16 Datasheet, PDF (8/33 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

8413S12I-100 Data Sheet
AC Electrical Characteristics
Table 7A. PCI Express Jitter Specifications, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
PCIe Industry
Minimum Typical Maximum Specification
t_j
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
14.27
24.35
86
t_{REFCLK_HF_RMS Phase Jitter RMS;}
(PCIe Gen 2) ^{NOTE 2, 4}
ƒ= 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.47
3.04
3.1
t_{REFCLK_LF_RMS Phase Jitter RMS; ƒ= 100MHz, 25MHz Crystal Input}
(PCIe Gen 2) ^{NOTE 2, 4}
Low Band: 10kHz - 1.5MHz
0.17
0.67
3.0
t_{REFCLK_RMS}
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
ƒ= 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.37
0.79
0.8
Units
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note
section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1 is 86ps peak-to-peak for a sample size of 10⁶ clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}
(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI
Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Table 7B. AC Characteristics, V_DD = 3.3V ± 5%, V_{DDO_[A:E]} = V_{DDO_F} = V_{DDO_G} = V_{DDO_QREF} = 3.3V ± 5%; or
V_DD = 3.3V ± 5%, V_{DDO_G} = V_{DDO_QREF} = 2.5V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Output
Minimum Typical Maximum
Q[A:E], nQ[A:E]
100
f_OUT
Output Frequency
QF
50
QG
125
QREF[0:1]
25
Units
MHz
MHz
MHz
MHz
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
©2016 Integrated Device Technology, Inc.
8
October 4, 2016