8413S12I-100_16 Datasheet, PDF (3/33 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

8413S12I-100 Data Sheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 18, 38
11
2, 3, 4, 5, 6,
7, 8, 9, 10,
12, 13, 16,
19, 36, 37,
54, 55, 72
14,
15
17
20, 39, 53
21
Name
GND
V_DDA
nc
XTAL_IN,
XTAL_OUT
REF_SEL
V_DD
PLL_SEL
Type
Power
Power
Unused
Input
Input
Power
Input
Pullup
Pullup
Description
Power supply ground.
Analog supply pin.
No connect.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Input source control pin. See Table 3B. LVCMOS/LVTTL interface levels.
Core supply pins.
PLL bypass control pin. See Table 3A. LVCMOS/LVTTL interface levels.
22
CLK
Input Pulldown Non-inverting differential clock input.
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
nCLK
OE_A
V_{DDO_A}
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
V_{DDO_B}
OE_C
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Pullup/
Pulldown
Pullup
Pullup
Pullup
Inverting differential clock input. Internal resistor bias to V_DD/2.
Active HIGH output enable for Bank A outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Active HIGH output enable for Bank C outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
41, 42
QC0, nQC0 Output
Differential output pair. HCSL interface levels.
43, 44
QC1, nQC1 Output
Differential output pair. HCSL interface levels.
45
V_{DDO_C}
Power
46
V_{DDO_D}
Power
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be connected
to 3.3V to use any of the HCSL outputs.
47, 48
49, 50
51
52
56
57, 58
QD0, nQD0
QD1, nQD1
OE_D
Output
Output
Input
I_REF
V_{DDO_E}
QE0, nQE0
Input
Power
Output
Pullup
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank D outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode Q[Ax:Ex], nQ[Ax:EX] outputs.
Bank E (HCSL) output supply pin. 3.3V supply.
Differential output pair. HCSL interface levels.
59, 60
61
QE1, nQE1
OE_E
Output
Input
Pullup
Differential output pair. HCSL interface levels.
Active HIGH output enable for Bank E outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
©2016 Integrated Device Technology, Inc.
3
October 4, 2016