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8413S12I-100_16 Datasheet, PDF (7/33 Pages) Integrated Device Technology – Clock Generator for Cavium Processors
8413S12I-100 Data Sheet
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_F = 3.3V ± 5%; or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.3
Input
REF_SEL, PLL_SEL, nMR,
IIH
High
OE_REF, OE_A, OE_B,
Current OE_C, OE_D, OE_E, OE_G
VDD = VIN = 3.465V
Input
REF_SEL, PLL_SEL, nMR,
IIL
Low
OE_REF, OE_A, OE_B,
VDD = 3.465V, VIN = 0V
Current OE_C, OE_D, OE_E, OE_G
-150
VOH
Output High Voltage
VOL
Output Low Voltage
VDDO_F = VDDO_G, VDDO_QREF =
3.465V, IOH = -12mA
2.6
VDDO_G, VDDO_QREF = 2.625V,
IOH = -12mA
1.8
VDDO_F = VDDO_G, VDDO_QREF =
3.465V or
VDDO_G, VDDO_QREF = 2.625V,
IOH = 12mA
Typical
Maximum
VDD + 0.3
0.8
10
0.6
Units
V
V
uA
uA
V
V
V
Table 4D. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
IIL
VPP
VCMR
Input High Current
CLK, nCLK
Input Low Current
CLK
nCLK
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-10
-150
0.15
0.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2. Common mode voltage is defined as VIH.
Typical
Maximum
150
1.3
VDD – 0.85
Units
µA
µA
µA
V
V
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz

pF
Table 6. Input Frequency Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_F = VDDO_G = VDDO_QREF = 3.3V ± 5%; or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FIN
Input
Frequency
CLK, nCLK
XTAL_IN, XTAL_OUT
25
MHz
25
MHz
©2016 Integrated Device Technology, Inc.
7
October 4, 2016