8413S12I-100_16 Datasheet, PDF (2/33 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

Block Diagram
8413S12I-100 Data Sheet
nMR
Pullup
PLL_SEL
REF_SEL
Pullup
Pullup
Pulldown
CLK
nCLK
Pullup/Pulldown
0
1
XTAL_IN
OSC
XTAL_OUT
IREF
VCO
100MHz
100MHz
100MHz
100MHz
0
1
100MHz
50MHz
125MHz
OE_REF
OTE: OE_A, OE_B, OE_C, OE_D, OE_E, OE_G, OE_REF have internal pull-up resistors.
OE_A
QA0
nQA0
QA1
nQA1
OE_B
QB0
nQB0
QB1
nQB1
OE_C
QC0
nQC0
QC1
nQC1
OE_D
QD0
nQD0
QD1
nQD1
OE_E
QE0
nQE0
QE1
nQE1
QF
OE_G
QG
QREF0
QREF1
©2016 Integrated Device Technology, Inc.
2
October 4, 2016