TSI352 Datasheet, PDF (73/183 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi352

6. Error Handling
73
6.3.3.1
Parity Error on Initial Delayed Write Request
When the Tsi352 detects a parity error on the write data for the initial delayed write request transaction,
the following events occur:
• If the parity error response bit corresponding to the initiator bus is set, the Tsi352 asserts TRDY_b
to the initiator and the transaction is not queued. If multiple data phases are requested, STOP_b is
also asserted to cause a target disconnect. Two cycles after the data transfer, the Tsi352 also asserts
PERR_b.
If the parity error response bit is not set, Tsi352 returns a target retry and queues the transaction as
usual. The PERR_b signal is not asserted. In this case, the initiator repeats the transaction.
• The Tsi352 sets the detected parity error bit in the status register corresponding to the initiator bus,
regardless of the state of the parity error response bit.
If parity checking is turned off and data parity errors have occurred for queued or subsequent
delayed write transactions on the initiator bus, it is possible that the initiator’s attempts of the
write transaction can not match the original queued delayed write information contained in
the delayed transaction queue. In this case, a master timeout condition can occur, possibly
resulting in a system error (P_SERR_b asserted).
Downstream Transactions
For downstream transactions, when the Tsi352 is delivering data to the target on the secondary bus and
S_PERR_b is asserted by the target, the following events occur:
• The Tsi352 sets the secondary interface data parity detected bit in the secondary status register, if
the secondary parity error response bit is set in the “Bridge Control Register—Offset 0x3C” on
page 151.
• The Tsi352 captures the parity error condition to forward it back to the initiator on the primary bus.
Upstream Transactions
For upstream transactions, when the Tsi352 is delivering data to the target on the primary bus and
P_PERR_b is asserted by the target, the following events occur:
• The Tsi352 sets the primary interface data parity detected bit in the status register, if the primary
parity error response bit is set in the “Primary Command Register—Offset 0x04” on page 124.
• The Tsi352 captures the parity error condition to forward it back to the initiator on the secondary
bus.
Integrated Device Technology
www.idt.com
Tsi352 User Manual
80D6000_MA001_03