TSI352 Datasheet, PDF (54/183 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi352

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3.3.2
3. Address Decoding
ISA Mode
The Tsi352 supports ISA mode by providing an ISA enable bit in the bridge control register in
configuration space (“Bridge Control Register—Offset 0x3C” on page 151). ISA mode modifies the
response of the Tsi352 inside the I/O address range in order to support mapping of I/O space in the
presence of an ISA bus in the system. This bit only affects the response of the Tsi352 when the
transaction falls inside the address range defined by the I/O base and limit address registers, and only
when this address also falls inside the first 64 kB of I/O space (address bits [31:16] are 0x0000).
When the ISA Enable bit is set, the following conditions are true:
• The Tsi352 does not forward downstream any I/O transactions addressing the top 768 bytes of each
aligned 1 kB block. Only those transactions addressing the bottom 256 bytes of an aligned 1 kB
block inside the base and limit I/O address range are forwarded downstream. Transactions above
the 64 kB I/O address boundary are forwarded as defined by the address range defined by the I/O
base and limit registers.
• The Tsi352 forwards upstream those I/O transactions addressing the top 768 bytes of each aligned
1 kB block within the first 64 kB of I/O space. The master enable bit in the command configuration
register must also be set to enable upstream forwarding (see “Primary Command Register—Offset
0x04” on page 124). All other I/O transactions initiated on the secondary bus are forwarded
upstream only if they fall outside the I/O address range.
• When the ISA enable bit is set, devices downstream of the Tsi352 can have I/O space mapped into
the first 256 bytes of each 1 kB chunk below the 64 kB boundary, or anywhere in I/O space above
the 64 kB boundary.
Tsi352 User Manual
80D6000_MA001_03
Integrated Device Technology
www.idt.com