TSI352 Datasheet, PDF (128/183 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi352

128
13. Register Descriptions
Bits
24
23
22
21
20
16:19
Name
DP_D
TFBBC
Reserved
DEV66
ECP
Reserved
Description
Data Parity Detected
This bit is set to 1 when all of the following are true:
• Tsi352 is a master on the primary bus.
• Signal P_PERR_b is detected asserted, or a parity error is
detected on the primary bus.
• The parity error response bit is set in the command
register.
Fast Back-to-Back Capable
Set to 1 to indicate that Tsi352 is able to respond to fast
back-to-back transactions on the primary interface.
Reserved. Returns 0 when read.
66-MHz Capable
Set to 1 to indicates that primary interface is 66- MHz
capable.
Enhanced Capabilities Port (ECP) Enable.
Reads as 1 in Tsi352 to indicate that Tsi352 supports an
enhanced capabilities list.
Reserved. Returns 0 when read.
Type
R/W1TC
R
R
R
R
R
Reset value
0x0
0x1
0x0
0x1
0x1
0x0
Tsi352 User Manual
80D6000_MA001_03
Integrated Device Technology
www.idt.com