TSI352 Datasheet, PDF (119/183 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi352

13. Register Descriptions
119
13.2
Register Map
The following table lists the register map for the Tsi352.
Table 30: Register Map
Offset
0x00
0x00
0x04
0x04
0x08
0x08
0x08
Name
Bits
Device ID
Vendor ID
31:16
15:0
Primary Status Register
Primary Command Register
31:16
15:0
Base Class Code
Subclass Code
31:24
23:16
Programming Interface Register 15:8
0x08
0x0C
0x0C
0x0C
Revision ID
Reserved
Header Type
Primary Latency Timer
7:0
-
23:16
15:8
0x0C
0x10-0x14
0x18
Cacheline Size
Reserved
Secondary Latency timer
7:0
-
31:24
0x18
Subordinate Bus Number
23:16
0x18
Secondary Bus Number
15:8
0x18
0x1C
0x1C
0x1C
0x20
Primary Bus Number
Secondary Status
I/O Limit
I/O Base
Memory Limit Address
7:0
31:16
15:8
7:0
31:16
0x20
Memory Base Address
15:0
See
“Device ID Register—Offset 0x00” on page 123
“Vendor ID Register—Offset 0x00” on page 123
“Primary Status Register—Offset 0x04” on page 127
“Primary Command Register—Offset 0x04” on page 124
“Base Class Code Register—Offset 0x08” on page 130
“Subclass Code Register—Offset 0x08” on page 130
“Programming Interface Register—Offset 0x08” on
page 129
“Revision ID Register—Offset 0x08” on page 129
-
“Header Type Register—Offset 0x0C” on page 133
“Primary Latency Timer Register—Offset 0x0C” on
page 132
“Cacheline Size Register—Offset 0x0C” on page 131
-
“Secondary Latency Timer Register—Offset 0x18” on
page 136
“Subordinate Bus Number Register—Offset 0x18” on
page 135
“Secondary Bus Number Register—Offset 0x18” on
page 134
“Primary Bus Number Register—Offset 0x18” on page 134
“Secondary Status Register—Offset 0x1C” on page 139
“I/O Limit Address Register—Offset 0x1C” on page 138
“I/O Base Address Register—Offset 0x1C” on page 137
“Memory Limit Address Register—Offset 0x20” on
page 142
“Memory Base Address Register—Offset 0x20” on
page 141
Integrated Device Technology
www.idt.com
Tsi352 User Manual
80D6000_MA001_03