TSI352 Datasheet, PDF (144/183 Pages) Integrated Device Technology – This chapter discusses the following topics about the Tsi352

144
13. Register Descriptions
13.3.24
Prefetchable Memory Limit Address Register—Offset 0x24
This section describes the prefetchable memory limit address register. This register must be initialized
by configuration software.
Byte enable P_CBE_b[3:0] = 00xxb
Register name: PCI_MIO_PM_LA
Reset value: 0x0001
Register offset: 0x24
Bits
7
6
5
4
3
2
1
0
31:24
23:16
PM_LA
PM_LA
ADD_LA_64
Bit
31:20
19:16
Name
PM_LA
ADD_LA_64
Description
Prefetchable memory limit address [31:20]
Defines the top address of an address range used by Tsi352
to determine when to forward memory read and write
transactions from one interface to the other. The upper 12
bits are writable and correspond to address bits [31:20].
The lower 20 bits of the address are assumed to be
0xFFFFF. The memory limit upper 32 bits register contains
the upper half of the limit address. The memory address
range adheres to 1MB alignment and granularity.
64-bit indicator
Bridge supports 64-bit addressing.
Type
R/W
R
Reset Value
0x0
0x1
Tsi352 User Manual
80D6000_MA001_03
Integrated Device Technology
www.idt.com