ICSSSTUAF32869A Datasheet, PDF (7/21 Pages) Integrated Device Technology – 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Terminal Functions
Signal
Group
Terminal
Name
Type
Description
Ungated
Inputs
DCKE, DODT SSTL_18 DRAM function pins not associated with Chip Select
Chip Select
Gated Inputs
D1...D14¹
SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW
Chip Select
Inputs
Re-Driven
Outputs
DCS, CSR
Q1A...Q14A¹,
Q1B...Q14B¹,
QCSnA, B
QCKEnA, B
QODTnA, B
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
LOW when a valid address/command is present.
SSTL_18
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock
Parity Input
PARIN
SSTL_18
Input parity is received on pin PARIN, and should maintain odd
parity across the D1:D14 inputs, at the rising edge of the clock,
one cycle after Chip Select is LOW.
Parity Output
PPO
SSTL_18 Partial Parity Output. Indicates parity out of D1-D14.
Parity Error
Output
PTYERR
Open Drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by in
total two clock cycles for compatibility with final parity out timing
on the industry-standard DDR2 register with parity (in JEDEC
definition).
Configuration
Inputs
C1
SSTL_18
When LOW, the register is configured as Register 1. When
HIGH, the register is configured as Register 2.
Clock Inputs CLK, CLK
SSTL_18
Differential master clock input pair to the register. The register
operation is triggered by a rising edge on the positive clock
input (CLK).
RESET
SSTL_18
Input
Asynchronous Reset Input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET also
resets the PTYERR signal.
Miscellaneous
Inputs
VREF
Input reference voltage for SSTL_18 inputs. Two pins
0.9V nominal (internally tied together) are used for increased
Inputsreliability.
VDD
Power Input Power Supply Voltage
GND
Ground Input Ground
1 This range does not include D1, D4, and D7, and their corresponding outputs.
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
ICSSSTUAF32869A
7095/13