ICSSSTUAF32869A Datasheet, PDF (14/21 Pages) Integrated Device Technology – 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
RESET
COMMERCIAL TEMPERATURE GRADE
DCS
CSR
CLK
n
n+1
n+2
n+3
n+4
CLK
D1 - D14⁽¹⁾
Q1 - Q14⁽¹⁾
PARIN ⁽²⁾
PPO ⁽²⁾
PTYERR ⁽²⁾
tSU
tH
tPD
CLK to Q
tSU
tH
tPD
CLK to PPO
tPD
CLK to PTYERR
tPD
CLK to PTYERR
NOTES:
1.This range does not include D1, D4, and D7, and their corresponding outputs.
2.PARIN is used to generate PPO and PTYERR.
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
14
ICSSSTUAF32869A
7095/13