ICSSSTUAF32869A Datasheet, PDF (2/21 Pages) Integrated Device Technology – 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Parity Implementation and Device Wiring
PARIN, W4
PPO, W8
PARIN
Register 1
(Front)
PPO, W4
Register 2
(Back)
PTYERR, W1
NC, A8
NC, A4
NC, A8
NC, A11
Block Diagram
VREF
PARIN
Set C=0 for Register 1, and C=1 for Register 2
(CS Active)
2
2
2
D
Q
R
2
PARITY GENERATOR
AND CHECKER
2
D
Q
D1
R
11
(1)
D14
D
Q
R
DCS0
CSR
D
Q
R
DCKE
D
Q
R
DODT
D
Q
R
RESET
CLK
CLK
NOTE:
1.This range does not include D1, D4, and D7, and their corresponding outputs.
PPO
PTYERR
Q1A
Q1B
Q14A⁽¹⁾
Q14B ⁽¹⁾
QCSA
QCSB
QCKEA
QCKEB
QODTA
QODTB
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
2
ICSSSTUAF32869A
7095/13