ICSSSTUAF32869A Datasheet, PDF (3/21 Pages) Integrated Device Technology – 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32869A
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Block Diagram
RESET
CLK
CLK
D2 - D3,
D5 - D6,
D8 - D14
11
VREF
LPS0
(Internal Node)
D ^CE
D ^CCEE
CLK
R
CE
CLK
R
D2 - D3,
11 ^{D5 - D6,}
D8 - D25
Parity
Check
COMMERCIAL TEMPERATURE GRADE
D2 - D3,
D5 - D6,
11 ^{D8 - D14}
11 ^{Q2 A- Q3A,}
Q5A - Q6A,
Q8A - Q14A
11 ^{Q2B - Q3B,}
Q5B - Q6B,
Q8B - Q14B
PARIN
2
0
D
1
CLK
R
D
CLK
R
CE
2 _PPO
2 _PTYERR
C1, C2
CLK
2-Bit
Counter
R
NOTE:
1.PARIN is used to generate PPO and PTYERR.
0
D
1
CLK
R
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
3
ICSSSTUAF32869A
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