ICS9DB403D Datasheet, PDF (7/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 1 and Gen 2

ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T_A =Tambient; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33^Ω, R_P=49.9^Ω, R_REF=475^Ω
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Current Source Output
Impedance
Zo¹
3000
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single ₆₆₀
ended signal using oscilloscope
math function.
-150
Max Voltage
Vovs
Measurement on single ended
Min Voltage
Vuds
signal using absolute value. -300
Crossing Voltage (abs) Vcross(abs)
250
Crossing Voltage (var) d-Vcross
Variation of crossing over all
edges
Rise Time
t_r
V_OL = 0.175V, V_OH = 0.525V
175
Fall Time
t_f
V_OH = 0.525V V_OL = 0.175V
175
Rise Time Variation
d-t_r
Fall Time Variation
Duty Cycle
d-t_f
d_t3
Measurement from differential
45
wavefrom
Skew, Input to Output
t_pdBYP
t_pdPLL
Bypass Mode, V_T = 50%
PLL Mode V_T = 50%
2500
-250
Skew, Output to Output
Jitter, Cycle to cycle
t_sk3
t_jcyc-cyc
V_T = 50%
PLL mode
Additive Jitter in Bypass Mode
PCIe Gen1 phase jitter
7
(Additive in Bypass Mode)
PCIe Gen 2 Low Band phase jitter
t_jphaseBYP
(Additive in Bypass Mode)
0
MAX UNITS NOTES
Ω
1
850
1,2
mV
150
1,2
1150 _mV
1
1
550 mV
1
140 mV
1
700
ps
1
700
ps
1
125
ps
1
125
ps
1
55
%
1
4500
250
50
50
50
10
ps
ps
ps
ps
ps
ps
(pk2pk)
1
1
1
1,3
1,3
1,4,5
ps
0.1 _(rms) 1,4,5
Jitter, Phase
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
ps
0.3 0.5 _(rms) 1,4,5
PCIe Gen 1 phase jitter
40
86
t_jphasePLL PCIe Gen 2 Low Band phase jitter
1.5
3
PCIe Gen 2 High Band phase jitter
2.7/ _3.1
2.2
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.}
3 Measured from differential waveform
4 _{See http://www.pcisig.com for complete specs}
5 _{Device driven by 932S421C or equivalent.}
6 _{First number is High Bandwidth Mode, second number is Low Bandwidth Mode}
ps _1,4,5
(pk2pk)
ps _1,4,5
(rms)
ps _1,4,5,6
(rms)
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 1 and Gen 2
7
ICS9DB403D REV L 10/07/09