ICS9DB403D Datasheet, PDF (19/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 1 and Gen 2

ICS9DB403D
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
Revision History
Rev. Issue Date Description
1. Updated electrical characteristics for final data sheet
A
8/15/2006 2. Corrected references to 8 outputs (should be 4)
B
5/22/2007 Updated Polarity Inversion Table.
1. Corrected SMBus table to eliminate non-existant outputs. This effects
bytes 1 and 2.
C 1/16/2008 2. Changed PWD notation to Default in SMBus descriptions
D 2/29/2008 Added Input Clock Specs
E
3/18/2008 Fixed typo in Input Clock Parameters
F
4/9/2008 Updated Input Clock Specs
G 8/19/2008 Corrected typos on Bytes 1 and 2.
Page #
-
2
11
6
6
6
11
1. Updated Electrical Characteristics to add propagation delay and phase
noise information.
2. Corrected SMBus to reference pin numbers for 403 instead of 803 device.
3. Removed references to OE controls that are not present on 403.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus interface
to work
6. Added foot note to Byte 1 about functionality of OE bits and OE pins.
H 8/26/2008 7. Corrected Block Diagram with proper OE pins indicated.
Various
I
11/26/2008 Updated SMBus table - Byte0:Byte3.
11
J
2/6/2009 Added Industrial temp. specs and ordering information.
Various
K
7/13/2009 Updated general description and block diagram
1
1. Clarified that Vih and Vil values were for Single ended inputs
2. Added separate Idd values for the 9DB403
L
10/7/2009 3. Added Differential Clock input parameters.
Various
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19