ICS9DB403D Datasheet, PDF (3/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 1 and Gen 2

ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Pin Decription When OE_INV = 0
PIN # PIN NAME PIN TYPE
1
VDD
PWR
2
SRC_IN
IN
3
SRC_IN#
IN
4
GND
PWR
5
VDD
PWR
6
DIF_1
OUT
7
DIF_1#
OUT
8
OE_1
IN
9
DIF_2
10
DIF_2#
11
VDD
OUT
OUT
PWR
12
BYPASS#/PLL
IN
13
SCLK
IN
14
SDATA
I/O
15
PD#
IN
16
DIF_STOP#
17
HIGH_BW#
18
VDD
19
DIF_5#
20
DIF_5
21
OE_6
22
DIF_6#
23
DIF_6
24
VDD
25
OE_INV
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
26
IREF
27
GNDA
28
VDDA
OUT
PWR
PWR
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal osc. (if any) are
stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 1 and Gen 2
3
ICS9DB403D REV L 10/07/09