ICS9DB403D Datasheet, PDF (12/19 Pages) Integrated Device Technology – Four Output Differential Buffer for PCIe Gen 1 and Gen 2

ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Byte 0 Pin #
Name
Control Function
Type
Bit 7
-
PD_Mode
PD# drive mode
RW
Bit 6
-
STOP_Mode
SRC_Stop# drive mode
RW
Bit 5
-
PD_Polarity
Select PD polarity
RW
Bit 4
-
Reserved
Reserved
RW
Bit 3
-
Reserved
Reserved
RW
Bit 2
-
PLL_BW#
Select PLL BW
RW
Bit 1
-
BYPASS#
BYPASS#/PLL
RW
Bit 0
-
SRC_DIV#
SRC Divide by 2 Select
RW
0
1
driven
Hi-Z
driven
Hi-Z
Low
High
Reserved
Reserved
High BW Low BW
fan-out
ZDB
x/2
1x
Default
0
0
0
X
X
1
1
1
SMBus Table: Output Control Register
Byte 1 Pin #
Name
Control Function
Type
0
1
Default
Bit 7
-
Reserved
Reserved
RW
Reserved
1
Bit 6 22,23
DIF_6
Output Enable
RW Disable Enable
1
Bit 5 19,20
DIF_5
Output Enable
RW Disable Enable
1
Bit 4
-
Reserved
Reserved
RW
Reserved
1
Bit 3
-
Reserved
Reserved
RW
Reserved
1
Bit 2
9,10
DIF_2
Output Enable
RW Disable Enable
1
Bit 1
6,7
DIF_1
Output Enable
RW Disable Enable
1
Bit 0
-
Reserved
Reserved
RW
Reserved
1
NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Byte 2 Pin #
Name
Bit 7
-
Reserved
Bit 6 22,23
DIF_6
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
Reserved
Bit 1
6,7
DIF_1
Bit 0
-
Reserved
Control Function
Reserved
DIF_6 Stoppable with OE6
Reserved
Reserved
Reserved
Reserved
DIF_1 Stoppable with OE1
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
Reserved
0
Free-run Stoppable 0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Free-run Stoppable 0
Reserved
0
SMBus Table: Reserved Register
Byte 3 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
X
X
X
X
X
X
X
X
IDT^TM/ICS^TM Four Output Differential Buffer for PCIe Gen 1 and Gen 2
12
ICS9DB403D REV L 10/07/09