ICS9250-27 Datasheet, PDF (7/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III^TM
Absolute Maximum Ratings
Core Supply Voltage
4.6 V
I/O Supply Voltage
3.6V
Logic Inputs
GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature
0°C to +70°C
Storage Temperature
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%, V_DDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP
MAX
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = 0 pF; Select @ 66 MHz
C_L = 0 pF; Select @ 100 MHz
C_L = 0 pF; Select @ 133 MHz
C_L = Max loads; Select @ 66 MHz
C_L = Max loads; Select @ 100 MHz
2
V_SS-0.3
-5
-5
-200
V_DD+0.3
0.8
5
2
-100
97
115
91
110
100
165
295
330
280
320
Operating Supply
Current
I_DD2.5OP
C_L = Max loads; Select @ 133 MHz
C_L = 0 pF; Select @ 66 MHz
C_L = 0 pF; Select @ 100 MHz
C_L = 0 pF; Select @ 133 MHz
C_L = Max loads; Select @ 66 MHz
C_L = Max loads; Select @ 100 MHz
300
395
16
19
25
35
26
40
19
30
34
50
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance¹
Transition time¹
Settling time¹
Clk Stabilization¹
Delay¹
I_DD3.3PD
I_DD.25PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_trans
T_s
T_STAB
t_PZH,t_PZL
t_PHZ,t_PLZ
C_L = Max loads; Select @ 133 MHz
C_L = Max loads
Input address VDD or GND
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From V_DD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
40
70
220
400
<1
10
12 14.318 16
7
5
6
27
45
5
5
5
1
10
1
10
1_{Guaranteed by design, not 100% tested in production.}
UNITS
V
V
µA
µA
mA
mA
mA
mA
µA
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
IDT^TM Frequency Generator and Integrated Buffers for Celeron & PII/III^TM
7
0395F—01/25/10