ICS9250-27 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III^TM
Truth Table
FS2 FS1 FS0
X00
X0 1
CPU
Tristate
TCLK/2
0 1 0 66.6 MHz
0 1 1 100 MHz
1 1 0 133 MHz
1 1 1 133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
Tristate
TCLK/3
66.6
MHz
66.6
MHz
66.6
MHz
66.6
MHz
PCI
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
SpreadSpectrum
(1=On/0=Off)
26 48MHz 1
25 48MHz 0
49 CPUCLK2
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
REF
Tristate
TCLK
14.318
MHz
14.318
MHz
14.318
MHz
14.318
MHz
IOAPIC
Tristate
TCLK/6
33.3
MHz
33.3
MHz
33.3
MHz
33.3
MHz
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
IDT^TM Frequency Generator and Integrated Buffers for Celeron & PII/III^TM
4
0395F—01/25/10