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ICS9250-27 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™
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ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
9
20
19
18
16
15
13
-
Name
3V66-2 (AGP)
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Undefined bit
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
X (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Bit7 ICS Reserved bit (Note 2)
Bit6 ICS Reserved bit (Note 2)
Bit5 ICS Reserved bit (Note 2)
Bit4 ICS Reserved bit (Note 2)
Bit3 ICS Reserved bit (Note 2)
Bit2 Undefined bit (Note 3)
Bit1 Undefined bit (Note 3)
Bit 0 FS0
FS1
0
0
0
0
1
0
0
0
1
Bit 0
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
Desctiption
CPUCLK SDRAM
MHz MHz
66.66 100.0
100.0 100.0
133.32 133.32
133.32 100.0
66.66 100.0
100.0 100.0
133.32 133.32
133.32 133.32
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
PCICLK IOAPIC
MHz MHz
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
33.33 33.33
PWD
0
0
0
0
0
X
X
0
Note 1
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU
is at the 133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free
during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3: Undefined bits can be written either as "1 or 0"
IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
5
0395F—01/25/10
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